Semiconductor device geometries have dramatically decreased in size since their introduction several decades ago. Modern semiconductor fabrication equipment routinely produces devices with 45 nm, 32 nm, and 28 nm feature sizes, and new equipment is being developed and implemented to make devices with even smaller geometries. The decreasing feature sizes result in structural features on the device having decreased spatial dimensions. The widths of gaps and trenches on the device narrow to a point where the aspect ratio of gap depth to its width becomes high enough to make it challenging to fill the gap with material.
Polycrystalline silicon (often shortened to polysilicon) is a material which has multiple uses in the production of microcircuitry and solar cells. Polysilicon is deposited most commonly by thermal chemical vapor deposition (e.g. LP-CVD). It has also been deposited using plasma-enhanced CVD (i.e. PE-CVD) as well as formed through recrystallization of amorphous silicon. In many applications, polysilicon is doped and used as a gate or electrode. In other applications, polysilicon is used for portion(s) of transistors themselves, in which case they may be doped or intrinsic. The diversity of applications requires flexible methods for depositing polysilicon conformally as well as non-conformally.
New deposition methods are required which offer the flexibility to vary the conformality of the deposition of a polysilicon layer. These new methods should also enable deposition at reduced substrate temperatures in order to stay within increasingly stringent thermal budgets.